1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and in particular, to a circuit capable of compensating an operation speed fluctuation.
2. Description of the Related Art
Conventionally, as disclosed in Vincent von Kaenel, Peter Macken, Marc G. r. Degrauwe, "A voltage Reduction Technique for Battery-Operated System", IEEE Journal of Solid State Circuits, vol. 25, No. 5, 1990, this type of technique for compensating a operation speed variation is used for compensating a circuit operation speed so as to be synchronized with an operation timing of an external clock when there is a device-parameter deviation or a device parameter change caused by an externally-supplied voltage and a temperature change due to heat dissipation.
FIG. 6 is a block diagram showing an example of conventional technique for compensating a operation speed variation.
Referring to FIG. 6, an internal voltage Vred is supplied to a power voltage terminal of an internal circuit 101 an to a voltage control oscillator 102.
The voltage control oscillator 102 outputs to a fixed N-divider 103 an oscillation frequency according to the voltage of the internal voltage Vred supplied.
The fixed N-divider 103 divides the high frequency inputted from the voltage control oscillator 102 by N (N is an integer) as an output signal to a phase comparator 104.
The phase comparator 104 compares the output frequency from the fixed N-divider 103 to an external clock frequency fin. If the clock frequency fin is higher, an Up signal is outputted to a charge pump 105, and if the fin is lower, a Down signal is outputted to a charge pump 105.
The charge pump 105, upon reception of the Up signal, increases a charge supply to a low-pass filter 106 at a following stage, and upon reception of the Down signal, decrease charge from the low-pass filter.
The low-pass filter 106 flattens the charge flow from the charge pump 105 for supplying a DC voltage Vred with little fluctuation to the internal circuit 101 and the voltage control oscillator 102.
That is, when an Up signal is supplied to the charge pump 105, the voltage Vred becomes higher, and when a Down signal is supplied, the voltage Vred becomes lower.
The internal circuit 101 as an ordinary logical circuit, operates at a higher speed as the internal voltage Vred supplied becomes higher, and at a lower speed as the internal voltage Vred becomes lower.
Moreover, the voltage control oscillator 102 outputs a higher frequency as the internal voltage Vred supplied becomes higher, and a lower frequency as the internal voltage Vred supplied becomes lower.
Consequently, even if there are device parameter deviations and an external supply voltage fluctuation or temperature change caused by heat of device, the internal voltage Vred is automatically controlled so that the output frequency of the voltage control oscillator 102 be just fin.times.N.
That is, if the output frequency of the voltage control oscillator 102 is designed to be fin.times.N for th internal voltage Vred at which the internal circuit 101 operates at a desired speed, irregularities of the operation speed of the internal circuit 101 can be compensated.
Next, explanation will given on the operation speed fluctuation compensation disclosed in Japanese Patent Publication (Unexamined) No. 8-223018. FIG. 7 is a block diagram showing an example of the device-deviation tolerance compensation technique disclosed in the aforementioned Publication.
Referring to FIG. 7, an internal circuit 201 and a delay circuit are supplied with a first internal voltage Vpp, a second internal voltage Vnn, a first well voltage Vpb, and a second well voltage Vbn.
The internal circuit 201 and the delay circuit 202 use the clock signal fin as an input signal and are operated by a power source voltage corresponding to a voltage difference between the first internal voltage Vpp and the second internal voltage Vnn. The internal circuit 201 and the delay circuit 202 are constituted by a plurality of logical gates consisting of P channel MOS (Metal-Oxide-Semiconductor) transistors using a first well voltage Vbp as a well voltage and N channel MOS transistors using a second well voltage Vbn as a well voltage.
The delay circuit 202 includes a plurality of basic gates (CMOS inverters) connected in a plurality of stages for generating an output signal in a predetermined time after the clock signal fin is inputted, so that the output signal is transmitted to a phase comparator 204.
The phase comparator 204 compares the clock signal fin to the output signal of the delay circuit 202. If phase of the clock fin is earlier, a Down signal is outputted from the phase comparator 204 to a charge pump 205, and if phase of the fin is later, an Up signal is outputted to the charge pump 205.
The charge pump 205, upon reception of the Up signal, increases a charge supply to a low-pass filter 206 of a following stage, and upon reception of the Down signal, decrease charge from the low-pass filter 206.
The low-pass filter 206 flattens the charge flow from the charge pump 205 so that a DC voltage Vpin with little fluctuation is supplied to a voltage converter 207.
The first voltage converter 207, following the input terminal voltage, generates an internal voltage Vpp from an external power voltage Vdd. For example, this circuit is a three-terminal regulator.
A difference between the first internal voltage Vpp and the second internal voltage Vnn is the power voltage. If the first internal voltage Vpp increases, the internal circuit 201 and the delay circuit 202 operate at a higher speed. On the contrary, if the first internal voltage Vpp is lowered, their operation speed is also lowered.
Moreover, most of the P channel MOS transistors have the first well voltage Vbp (fixed voltage) as their well terminal voltage and the first internal voltage Vpp as their source terminal voltage. Accordingly, if the first voltage Vpp is increased, a threshold voltage VthP of the P channel MOS transistors is lowered.
Thus, increase of the internal voltage Vpp results in a high-speed operation of the internal circuit 201 and the delay circuit 202, and lowering of VPP results in a low-speed operation of the internal circuit 201 and the delay circuit 202.
Consequently, even if there is device parameter deviation and an external voltage Vdd fluctuation or a temperature change, the internal voltage Vpp is automatically controlled so that a delay time from a clock input to the delay circuit 202 to an output of an output signal from the delay circuit 202 is equal to the clock cycle.
That is, if the semiconductor integrated circuit is designed in advance so that the delay time of the delay circuit 202 is equal to the delay time of the internal circuit 201, it is possible to compensate operation speed variations or fluctuations of the internal circuit 201.
In FIG. 7, the second internal voltage Vnn and the second well voltage Vbn are grounding voltage. However, it is also possible to provide a second voltage converter between the grounding voltage and the second internal voltage Vnn.
Here, if the second internal voltage Vnn is made to change, the threshold voltage VthN of the N channel transistors is changed. Accordingly, in comparison to the case when only the first voltage converter or controller 207 is controlled, a wide range is available for operation speed compensation of the internal circuit 201.
However, the aforementioned conventional technique for compensating a operation speed variation have problems described below.
(1) The first problem is that it is impossible to correctly compensate the operation speed of the internal circuit. PA1 (2) The second problem is that it is especially difficult to apply the conventional technique to circuits including analog circuits or a large wiring delay in their critical paths, dominating a delay time from an input to an output of an entire chip. PA1 (3) The third problem is that a delay circuit or a voltage control oscillator or a fixed N-divider require a considerable area and therefore application of the conventional technique for compensating a operation speed variation costs much. PA1 (4) The fourth problem is that the voltage control oscillator and the delay circuit consume a considerable power.
This is because of an assumption that an output frequency of a voltage control oscillator and a delay time of the delay circuit consisting of basic gates connected in a plurality of stages are considered as the operation speed of the internal circuit. There is a certain position correlation between the internal circuit speed and the output frequency of the voltage control oscillator or the delay time of the delay circuit using transistors arranged on a single chip. However, it is clear that different speeds are measured in principle. To design a circuit considering a difference of these operation speeds, it is necessary to anticipate an operation margin for them.
That is, an operation speed can be estimated by output frequency of the voltage control oscillator or the delay time of the delay circuit reflects only fluctuations of the transistor characteristics.
In rough approximation, in a case when a transistor gate delay is dominant, if ON-current of transistors is decreased into half by a device-parameter deviation or a temperature change, then the delay time of the circuit approximately doubles.
However, in a circuit where a wiring delay is dominant or in an analog circuit handling a fine amplitude, the relationship between the ON-current of their transistors and the circuit delay time is not linear, because the circuit delay time is also affected by the variation of a wiring thickness and the little deviation of ON-current between adjacent transistors.
Accordingly, when applying the aforementioned conventional technique to a circuit as a critical path, including an analog circuit or a circuit in which a wiring delay is critical, the correlation between an operation speed of an internal circuit and an output frequency of a voltage control oscillator or a delay time of a delay circuit is considerably lowered, causing a fatal error.
As the design-rule becomes smaller, a wiring delay becomes more dominant in most circuits. This tendency is considered to be further accelerated, and there will be left almost no circuits which can apply the technique for compensating a operation speed variation.
The reason is as follows. In principle, the multi-stage connection of basic logical gates should have a delay time identical to that of an internal circuit critical path. Accordingly, as the internal circuit size increases, the number of stages is also increased.
The technique for compensating a operation speed variation has little merit to apply it unless it is applied to a comparatively large circuit in size. Consequently, the delay circuit can be large in many cases.
Moreover, the voltage control oscillator and the fixed N-divider also require a certain area although not so large as the delay circuit.
As has been described in the circuit operation using the conventional technique for compensating a operation speed variation, the voltage control oscillator is operated at the frequency of the external clock fin multiplied by N, except for the power consumption of the internal circuit. Accordingly, a great power is consumed.
The delay circuit has also a number of stages connected because of the aforementioned reason, where a signal transition occurs with each clock input. Accordingly, the power consumption cannot be small.
Moreover, the power supply to the voltage control oscillator and the power supply to the internal circuit are both realized by a single charge pump. Accordingly the output power required of the charge pump is also very large.
The aforementioned power consumption in itself is a loss because it does not contribute to the performance of the internal circuit.